A typical memory array is constructed of multiple memory cells arranged in a matrix of columns and rows which are respectively correlated to bit lines and word lines. Each individual memory cell is located at the intersection of a particular word line and bit line. The memory cell is accessed by referencing that location or address. Each memory cell can hold one of two values, a "1" or a "0". After a memory array is manufactured it must be tested in order to identify which memory cells, if any, are defective. The primary concern is to detect faults that will cause a memory device to function incorrectly. Faults typically tested for include stuck-at faults, coupled-cell faults and single-cell pattern-sensitivity faults.
One method of testing memory devices is to write a specific pattern of "1"s and "0"s and then read the cells to see if there are any unexpected values. For example, a checkerboard pattern can be used to test for single-cell pattern sensitivity faults. A pattern of alternating "0"s and "1"s evaluates individual cells for defects such as charge leakage. Writing a "1" to one cell and "0"s to the surrounding cells tests the first cell's ability to hold the charge. In another example, row-stripes and column-stripes patterns may be used to test coupled-cell faults. Most test procedures address the set of faults most likely to occur rather than attempting to identify every possible fault, incorporating the appropriate series of test patterns.
Conventional memory testing is primarily performed in one of three methods. The first method uses automatic test equipment (ATE). According to this method all test-related circuitry and control and test data is external to the memory device. ATE testing is only performed on memory devices before they are incorporated into a system or other structure. The second test method, called built-in self-test (BIST), incorporates the test circuitry and data into the chip along with the memory device or devices. BIST allows the memory array to be tested at any point in the memory device's useful life. The third method of testing is a hybrid of the other two methods. Referred to as `designed for testability` (DFT), this method implements parts of the test circuitry on the chip, the rest being provided externally in a conventional application of hardware and control and test data. The ever-increasing costs of testing memory devices demands continuing advancements in test methods and procedures.
There are tradeoffs associated with each type of memory test method. ATE testing may be slower than the others and usually only provides for testing memory devices before they are integrated into a system. ATE testing provides no on-going verification of memory integrity. The benefit of ATE testing is that none of the valuable die real estate on the chip is taken up with testing circuitry--the entire chip area can be dedicated to the memory function.
DFT may be faster than ATE testing by virtue of the fact that the most memory cell input/output intensive circuitry is incorporated into the device itself. So, even though a portion of the test circuitry and data is still external to the memory device, the test processing is faster than that achieved with ATE processing. The DFT method also minimizes the impact on available die real estate by selectively incorporating test circuitry into the memory device.
BIST incorporates all required test circuitry and control and test data in the memory device itself, which has the effect of either reducing the area available for memory cells or forcing an increase in the overall size of the die. Activating the BIST circuitry also requires additional control signals. When additional pins are fabricated into the device the user can test the chip during its operational life. Since all test circuitry is incorporated into the device, the device spends much less time on the test equipment during the manufacturing process. BIST provides memory device testing that is both easier and faster than testing methods external to the memory device. BIST devices are used primarily for embedded memories where neither the address, read/write, nor data input lines are externally observable. Depending upon the BIST architecture, which determines when the testing actually occurs, memory access times may be impacted by the self-test processing. Unlike DFT, BIST can only perform algorithms built into the BIST hardware. BIST is currently the preferred method, however. The increase in hardware overhead and the inflexibility with regard to test algorithms is the accepted cost of achieving the significant reduction in test times, as well as the capability to perform BIST without external support and at the operational speed of the circuit.
In a conventional memory array, an external read or write operation is limited in the number of memory cells which can be addressed at one time. As a result, testing methods such as ATE and non-concurrent BIST, which write to and read from every memory cell, require a larger number of external cycles to test a memory device. Reading from or writing to a memory cell is relatively slow, leading to the situation where conventional testing techniques are less efficient because of the large number of external cycles. There is a need in the art for a test method which provides the same level of fault coverage in a reduced number of external read/write cycles. There is a further need in the art to provide a way to improve the performance of memory tests, thereby increasing the efficiency of the manufacturing process and expanding the ability to incorporate more extensive algorithms in the selected test method by using a test method which provides the same level of fault coverage in a reduced number of external read/write cycles.
One partial solution is presented by Sang H. Han and Miroslaw Malek in Two-Dimensional Multiple-Access Testing Technique for Random-Access Memories, 248 Proc. IEEE Int. Conference on Computer Design (1986). Their method proposes three test access modes and a modified address decoder which can be set to simultaneously select k output lines. Mode-0 is the conventional `one access per memory cell` process. Mode1 accesses k memory cells in one selected row at a time. Mode2 allows the test to access k cells in each of k rows at a time. Mode1 proved to speed up the test by k times, and Mode2 by k.sup.2 times. Ham's system provides some relief to the burden of memory testing, but the system is limited to reading or writing blocks of data according to the number of input lines available, providing only an incremental improvement in test speed. As a result, Han's and Malek's system provides only partial relief to the ever-increasing cost of testing. There remains a need to improve test performance.
In 1989, Ranier Kraus, et al. in Design for Test of Mbit DRAMs, 316 Proc. IEEE Int. Test Conference (1989), presented another partial solution which increased the performance of BIST procedures by as much as 75% for 4 Mbit DRAM devices. Kraus' process also executes at three levels or modes. In Mode1, predefined test patterns are written into the entire memory array and tested automatically in parallel. Since an internal address counter is used, this method is the fastest of the three, having the least number of external cycles. Mode2 is more flexible, allowing patterns to be assembled individually by addressing each word line externally. This process is much slower than Mode1 because it has a significantly increased number of external cycles over Mode1. Mode3 is the worst performer of the three modes. It tests margins and is used in conjunction with Mode1, Mode2, or any conventional test. Kraus' method requires circuitry comprising a test comparator, a test pattern generator, and a modified column predecoder and column decoder. At the 4 Mbit level this translates to about 1% of the chip area being dedicated to the test circuitry, except in cases where all bits are either "1" or "0", in which case a parallel read or write can be performed in two external cycles.
Kraus was able to drastically improve the time required to test memory devices, but only by incurring significant cost of additional manufacturing to incorporate the test circuitry into the chip, reduced die real estate available for memory cells, and inflexibility due to the requirement that the test patterns be predefined into the test pattern generator. Thus the cost of testing was not so much reduced by Kraus as shifted. What is still needed is a test method which has less impact on die real estate and which maintains or improves upon the test processing speed. More flexibility in test logic is also needed, such that test patterns may be developed and integrated into the test processing at any point. Kraus' system is employed primarily in BIST devices. What is needed is a test method which achieves the same or similar performance improvements in all test architectures (ATE, DFT, and BIST), reducing the cost of memory device testing.